The amount of processing performed per clock cycle by a processor is subject to change as the associated computations become more intensive. During low load periods, relatively few execution units such as multiply-and-accumulate (MAC) units are active in each processor clock cycle. But in response to sudden load changes, the number of active execution units may increase dramatically. The current demanded by the processor from its power supply rail will thus change in concert with the change in processing load. The resulting increase in current demand by the processor may cause its power supply voltage to droop undesirably, resulting in fault conditions.
It is thus conventional to lower a processor's clock frequency during periods of increased processing demand. For example, the clock frequency may be halved during such increased load periods. But lowering the clock frequency by too much results in the power supply voltage increasing undesirably, which leads to fault conditions such as hold violations. Conversely, lowering the clock frequency by too little results in low voltage fault conditions. Prior art load balancing techniques thus wavered between power distribution network (PDN) fault conditions resulting from too-high of a power supply voltage and fault conditions resulting from too-low of a power supply voltage.
Accordingly, there is a need in the art for improved load step balancing of the processor clock frequency in response to processor load increases.